1. Technical Field
Various embodiments of the present disclosure generally relate to semiconductor systems and methods of operating the same and, more particularly, to semiconductor systems performing a double-write operation and methods of operating the semiconductor systems.
2. Related Art
Nonvolatile memory devices retain their stored data even when power supply is interrupted, and data storage units including the nonvolatile memory devices are widely used in portable systems such as smart phones, digital cameras, or computers. The nonvolatile memory devices, particularly, NAND-type flash memory devices have been developed using multi-level cell (MLC) techniques and advanced process techniques to increase the integration density of the NAND-type flash memory devices. The MLC techniques have been proposed to increase the number of bits which are capable of storing data in a single cell, and the advanced process techniques have been proposed to reduce a minimum feature size of patterns constituting memory cells of semiconductor devices. Recently, three-dimensional and vertical cell structures have been developed to overcome the limitation of planar-type memory cell array structures in which memory cells are two dimensionally arrayed and to more efficiently increase the integration density of the NAND-type flash memory devices.
The process techniques for forming fine patterns and the MLC techniques for increasing the number of bits in a limited area may lead to degradation of the reliability of the NAND-type flash memory devices. This is because cell-to-cell interference occurs if a pattern size is reduced and a data error easily occurs if multi-bits are realized in a single cell using the MLC techniques. Meanwhile, in case of the nonvolatile memory devices such as phase change random access memory (PCRAM) devices, magnetoresistive RAM (MRAM) devices, nano floating gate memory (NFGM) devices, resistive RAM (RRAM) devices or polymer RAM devices, a read margin for recognizing a difference between a datum “0” and a datum “1” may be relatively narrow due to the nature of cells. Thus, the nonvolatile memory devices including the PCRAM devices, the MRAM device, the NFGM devices, the RRAM devices and the polymer RAM devices may exhibit a relatively high error rate as compared with the NAND-type flash memory devices even though a single level cell (SLC) structure is employed therein.
Errors, for example, soft errors occurring due to the nature of cells of the nonvolatile memory device during a write operation are referred to as write errors. One of various methods of suppressing write errors is to perform a double-writing operation that writes the same data into the same memory cell more than once. However, if the double-writing operation is performed, the number of accesses to the memory cells increases to cause degradation of endurance and function of the memory cells.